The present invention relates to a method for forming a semiconductor device, and more particularly to a semiconductor device and a method for forming the same, which reduces a defective pattern from occurring in bit lines that have different widths so as to accurately connect a bit line to a bit line contact and to increase a margin of a storage electrode contact.
In recent times, the demand for implementing a high-capacity dynamic random access memory (DRAM) has rapidly increased. However, there is difficulty in increasing a chip size, resulting in a limitation in increasing storage capacity of the DRAM. The larger the chip size, the fewer the number of chips on each wafer, resulting in a reduction in productivity. Therefore, in recent times, many researchers are conducting intensive research into a method for reducing a cell region by varying a cell layout so as to form a large number of memory cells on one wafer. By such efforts, a semiconductor layout is rapidly changing from a 8F2-layout to a 6F2-layout.
A 6F2-layout device means a semiconductor device having a 6F2-sized unit cell in which the length in the direction of a bit-line is 3F and the length in the direction of a word-line is 2F such that a total area of 6F2 is given. Therefore, as the unit-cell area is rapidly changing from 8F2 to 6F2, the degree of integration is also increasing. Each of the DRAM devices based on the 6F2 layout has an oblique active shape A, and two unit cells are generally formed in one active region. Two storage electrode contact plugs are arranged between bit lines, and pass through a bit line contact in the active region, such that the 6F2-layout DRAM device has a higher degree of integration than the 8F2-layout DRAM device.
FIG. 1A is a plan view illustrating a conventional semiconductor device, and FIG. 1B is a cross-sectional view illustrating the semiconductor device taken along the line X-X′ of FIG. 1A.
Referring to FIG. 1A, a 6F2-layout cell region includes a plurality of active regions A arranged to have a predetermined angle with respect to a bit line 18, a plurality of word liens (not shown) spaced apart from each other at intervals of 1F, and a plurality of bit lines 18 formed on the word lines while being spaced apart from each other at intervals of 1F.
In more detail, if a cross-sectional view is taken along line X-X′ in the semiconductor device of FIG. 1A, FIG. 1B is obtained.
Referring to FIG. 1B, the conventional semiconductor device includes an interlayer insulating layer 14 formed on a semiconductor substrate 10 having an active region defined by a device isolation layer 12, a bit line contact hole 16 formed in the interlayer insulating layer 14, and a bit line 18 burying the bit line contact hole 16. In this case, a word line, a landing plug, and an interlayer insulating layer may be further formed on the semiconductor substrate 10, and a detailed description thereof will be omitted herein for convenience of description.
The bit line 18 illustrated in FIG. 1A has a non-uniform width, and is designed to have a larger width where the bit line contact hole 16 is located. This is done so that the bit line can completely cover the bit line contact hole 16. Therefore, the width of the bit line 18 according to the related art is not set to the same value in all regions, and has different widths according to the presence or absence of the bit line contact hole 16.
However, it is difficult to implement the above-mentioned pattern. Particularly, in order to implement an exposure mask for defining the above-mentioned pattern, a semiconductor device must be designed in units of a small-sized segments. This requires a much longer production time and results in an increase in production cost. Although if it is assumed that the above-mentioned pattern is implemented on an exposure mask, it is difficult to perform patterning based on this pattern due to the reduction of a process margin.
FIG. 2 illustrates a patterning image based on a bit line exposure mask according to the related art.
As can be seen from FIG. 2, a pattern, in which a plurality of narrow-width parts and a plurality of wide-width parts are repeatedly arranged, has a very low process margin. This low process margin may cause a defective pattern F (e.g., a disconnection of the pattern) at any of the narrow-width sections. In the case of increasing a thickness of the bit line 18 in consideration of the bit line contact hole 16, a margin of a storage electrode contact formed in a post-process is decreased. This may cause the bit line to touch the storage electrode contact, resulting in the occurrence of a defective part in the semiconductor device.